The present invention generally pertains to digital signal processing and is particularly directed to an improvement in decoding systems that are used to decode convolutionally encoded digital data streams.
Digital data streams are convolutionally encoded to enhance forward error correction, as described in a paper entitled "Error Control" by Joseph P. Odenwalder, published in "Data Communications, Networks, and Systems", Thomas C. Bartee, Ed. (Indianapolis: Howard W. Sams, 1985) at Chapter 10, pages 289-354.
An example of a convolutional encoder is shown in FIG. 1. A digital data stream is convolutionally encoded by shifting the data stream 10 through a shift register 12 having a given number of stages, with bits of the data stream from given stages of the shift register being tapped and provided to a number of exclusive-OR (XOR) gates 14, 16 from which an encoded digital data stream is provided as a combination of I and J components. A convolutional encoder may include a greater number of XOR gates and/or a greater number of shift registers than in the example shown in FIG. 1. The given number of stages of the shift register 12 is commonly referred to as the "constraint length". Polynomial binary codes determine the particular stages of the shift register from which bits of the registered data stream are provided to a given XOR gate 14, 16. These polynomial codes are sometimes referred to as "code taps". In the example of FIG. 1, the constraint length is seven, the polynomial code for the XOR gate 14 is 1111001 and the polynomial code for the XOR gate 16 is 1011011.
A convolutionally encoded data stream is decoded by a data processor that processes the encoded data stream in accordance with the given constraint length and in accordance with the selected polynomial codes. Preferably the convolutionally encoded data stream is decoded in accordance with an algorithm described in a paper entitled "Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm" by Andrew J. Viterbi, published in "IEEE Transactions on Information Theory", Vol IT-13, no. 2, Apr. 1967, at pages 260-269. Decoders that use the Viterbi decoding algorithm are known as Viterbi decoders.
A Viterbi decoder is a path maximum likelihood decoder which provides forward error correction by employing a convolutional decoding scheme that typically provides four to five dBs of coding gain at a 10.sup.-5 bit error rate compared to unencoded systems. Thus, less power is required in the system to obtain an equivalent bit error rate. The Viterbi decoder works in conjunction with an interleaver which spreads each bit of baseband data over many bit times. The correlation of the received data symbol stream allows the decoder to choose the most probable state of the encoder even though the communications channel is corrupted by noise.
The use of Viterbi decoders for decoding data that has been convolutionally encoded in accordance with different fractional-rate codes and modulated for transmission by different modulation techniques is also described in the aforementioned paper by Odenwalder and in a paper entitled "Development of Variable-Rate Viterbi Decoder and Its Performance Characteristics" by Yukata Yasuda, Yasuo Hirata, Katsuhiro Nakamura and Susumu Otani, published in Sixth International Conference on Digital Satellite communication, Sep. 19-23, 1983" at pages XII-24 to XII-31.